1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a capacitor structure of a semiconductor device and a method of manufacturing the same, which has a suitable capacitance for use in the highly integrated device.
2. Discussion of the Related Art
In general, as the integration of a semiconductor device (such as a dynamic random access memory (DRAM)) increases, the area available to the capacitor becomes more limited. Each memory cell is manufactured by forming a transistor and a capacitor, which are active elements, on a substrate of limited area. According to the already determined design rule, the capacitor must be formed on a substrate where the transistor occupies a fixed area. Thus, it is difficult to manufacture a memory cell having a capacitor with a large capacity since the area occupied by the capacitor is decreased to that extent.
In order to overcome the limited area and obtain a capacitor having a capacitance suitably large enough for a highly integrated device, capacitors having a three-dimensional structure such as a stacked, a trench, a cylindrical, and a fin structure are used. If such a three-dimensional structure is used, a problem arises with respect to the reliability of the capacitor's dielectric film.
When a capacitor having the conventional three-dimensional structure is manufactured, the capacitor dielectric film will normally be composed of oxide-nitride-oxide (ONO). The problem with the ONO film, however, is its limited dielectric constant. Thus, even if the capacitor is manufactured having the conventional three-dimensional structure, the capacitor structure needs to become more complex as the integration is increased in order to obtain the desired capacitance. Accordingly, the ONO film is not a very suitable dielectric.
It should also be noted that if the thickness of the capacitor dielectric film is decreased, the capacitance can be increased. Thus, using a thin film is important not only because it will enable the device to be further miniaturized, but also because it will improve the device's capacitance. For example, in the 256 Mb DRAM, the effective thickness of the dielectric film must be reduced to about 3 nm or less using a SiO.sub.2 film.
However, research indicates that the effective thickness of the ONO film used now is limited to about 4 nm even if the nitridation anneal process is performed on it (refer to P. J. Wright and K. C. Saraswat, "Thickness limitation of SiO.sub.2 gate dielectrics for MOS ULSI", IEEE Trans. on Electron Devices, vol. 37, no. 8, 1990). Accordingly, where the ONO film is used in a capacitor, the structure of the capacitor storage node needs to become more complex in order to obtain a large capacitance.
Such complexity causes a severe topology problem in the stacked capacitor (such as the cylindrical structure or the fin structure), thereby requiring a high level of planarization technology. Even if planarization is accomplished, it is difficult to perform the subsequent process. For example, a contact hole having a large difference in depth must be filled in the subsequent wiring process. Further, where the capacitor has a trench structure, a high aspect ratio is present. Therefore, it is difficult to perform the etching process to form the trench, the cleaning process, and the silicon-filling process during the manufacturing of the opposite electrode within the trench.
Two types of manufacturing methods have emerged as methods for solving the aforementioned problems. The first method manufactures a storage node using a hemispherical grained silicon (HSG). Under this method, the surface of the chemical vapor deposition (CVD) silicon used as a capacitor storage node is formed into a rugged morphology instead of a smooth morphology. This increases the effective capacitor surface area in the capacitor region, although the area is still limited by the design and structure of the capacitor and semiconductor.
When the above described CVD silicon is deposited at a temperature of about 600.degree. C. or more, it has a smooth surface morphology such as with polycrystalline silicon. However, if the CVD silicon is deposited at a temperature of about 550.degree. C. or lower, and is heat-treated at temperatures around 580-600.degree. C., a rugged surface morphology is obtained whereby the hemispherical silicon grain protrudes. This hemispherical silicon grain increases the effective capacitor area to about 1.8-2.0 times that of the silicon surface of smooth morphology. Thus, a large capacitance can be obtained.
However, even if a HSG of good quality is obtained through the above described method, when the ONO film is used as the capacitor dielectric film, a capacitance of only about 9.1 fF/.mu.m.sup.2 can be secured with a high-step difference of about 0.8 .mu.m. In the case of a capacitor having the cylindrical structure, a high-step difference of about 1 .mu.m or more is necessary. Thus, the problem of having to increase the complexity of the capacitor arises again.
The second method that has emerged uses a capacitor dielectric film having a large dielectric constant (.sup.- r) (e.g., tantalum pentaoxide (Ta.sub.2 O.sub.5) (.sup.- r.24), PZT (.sup.- r.2000), BST (.sup.- r.300), and the like). The problem with these dielectrics is that if they are applied as a thin film, the dielectric constant is reduced rapidly and the leakage current is increased. This phenomenon will be described below.
In general, Ta.sub.2 O.sub.5 uses a penta-ethoxytantalum (Ta(OC.sub.2 H.sub.5).sub.5) as a source of Ta and injects O.sub.2 gas to form an oxide film. The thin film is then formed using the low pressure chemical vapor deposition (LPCVD) method, the plasma-enhanced CVD method, or the electron cyclotron resonance (ECR) CVD method.
The dielectric constant of Ta.sub.2 O.sub.5 is approximately 22-28, which is about 6 times that of SiO.sub.2. Further, if the proper heat treatment is performed after forming the thin film, the leakage current decreases to about 10.sup.-9 -10.sup.-7 A/cm.sup.2 under an electric field of 4 MV/cm. This particular type of dielectric is thus appropriate for use in the capacitor of a highly integrated memory device.
However, where silicon is used as the storage node a further complication can arise. When depositing the silicon, oxidation of its surface cannot be avoided, and a SiO.sub.2 film forms. Further, if heat treatment is performed after depositing the silicon, the SiO.sub.2 film grows all the more. When such a SiO.sub.2 film forms, the dielectric constant decreases and the desirable capacitance cannot be obtained.
One previously proposed solution to this problem was to nitrify the surface of the silicon layer constituting the storage node to form a silicon nitride film on the surface portion, followed by the depositing of the Ta.sub.2 O.sub.5 film. As a result, improvements were reported in the dielectric constant, leakage current, and time dependent dielectric breakdown (TDDB) as compared to when the silicon layer is not nitrified (refer to "Satoshi Kamiyana, Pierre-Yves Lesaicherre, Akihiko Ishitana, Akir Sakai, Akio Tanikawa, and Iwao Nishiyama, Extended Abstracts of the 1992 International Conference on Solid Devices and Materials, pp. 521-523", "P. C. Fazan, V. K. Mathews, R. L. Maddox, A. Ditali, N. Sandler and D. L. Kwong, Extended Abstracts of the 1992 International Conference on Solid Devices and Materials, pp. 697-698).
In addition, there is a method where the capacitance can be increased about 70% without a decrease in reliability. This is accomplished by forming the surface of the silicon electrode into a rugged morphology and using Ta.sub.2 O.sub.5 as the capacitor dielectric film (refer to H. Watanabe, T. Tatsumi, T. Niiono, A. Sakai, S. Adachi, K. Koyama and T. Kikkawa, Extended Abstracts of the 1991 International Conference on Solid Devices and Materials, pp. 478-480). In this case, the capacitance is about 12.5 fF/.mu.m.sup.2. Thus, it is possible to apply the Ta.sub.2 O.sub.5 film so long as no reproducibility problem occurs.
However, if the silicon layer is used as the lower electrode of the capacitor in the above structure, the dielectric constant of the Ta.sub.2 O.sub.5 film decreases due to the oxide or nitride film formed by the oxidation or nitridation, regardless of the surface morphology. Thus, large capacitance cannot be obtained.
Due to the aforementioned problems another type of capacitor has been proposed. In this capacitor structure, a refractory metal (e.g., tungsten (W), titanium nitride (TiN), molybdenum (Mo), etc., or a refractory metal silicide, e.g., tungsten silicide (WSi.sub.2), tantalum silicide (TaSi.sub.2), cobalt silicide (coSi.sub.2), etc.) is used as the lower electrode instead of the silicon layer. Accordingly, the inherently high dielectric constant of the high dielectric can be obtained, thereby increasing the effective area of the capacitor. This structure will be described below with reference to the attached drawings.
As shown in FIG. 1, the capacitor is comprised of a semiconductor substrate 1 wherein an impurity diffused region 2 is formed. An insulating film 3 is formed on the semiconductor substrate 1 with a contact hole 4 (of FIG. 2a). A Ti layer 5a is formed on the insulating film 3 and in the contact hole 4 (of FIG. 2a). A TiN layer 6 is formed on the Ti layer 5a and fills the contact hole 4 (of FIG. 2a). A tungsten film 7 is formed on the entire surface of the outer side of the TiN layer 6 and the Ti layer 5a. A dielectric film 8 is formed on the surface of the tungsten film 7, and an upper electrode 9 is formed on the entire surface of the substrate.
A method of manufacturing the aforementioned conventional capacitor will be described with reference to FIGS. 2a to 2e.
As shown in FIG. 2a, a semiconductor substrate 1, wherein an impurity diffused region 2 is formed in the surface, is prepared. An insulating film 3 is then formed on the semiconductor substrate 1 and is etched selectively to form a contact hole 4 and to expose impurity diffused region 2.
As shown in FIG. 2b, a Ti layer 5 and a TiN layer 6 are sequentially formed on the insulating film 3 and the impurity diffused region 2. The Ti layer 5 is deposited to maintain the ohmic contact with impurity diffused region 2. The TiN layer 6 is deposited to a thickness of about 0.5-1.0 .mu.m.
As shown in FIG. 2c, layers 5 and 6 are patterned to form a lower electrode using the lithography process.
As shown in FIG. 2d., tungsten is selectively deposited to a thickness of about 50-150 nm on the outer surface of the Ti layer 5a and the TiN layer 6a to form a tungsten film 7. The tungsten is deposited by using WF.sub.6 --H.sub.2, or WF.sub.6 --SiH.sub.4 --H.sub.2 at a temperature of 250-450.degree. C., through the LPCVD method. As a result, the tungsten film 7 has a rugged surface.
As shown in FIG. 2e, a capacitor dielectric film 8, e.g., a Ta.sub.2 O.sub.5 film, is formed on the entire surface of the tungsten film 7, and then heat treatment is performed. Lastly, an upper electrode 9 is formed on the entire surface of the substrate, to complete the capacitor. This upper electrode is a refractory metal such as TiN, Mo, Co, Ta and W, or a metal silicide.
The conventional capacitor manufactured as described above has the following problems.
As shown in FIG. 2d, when the tungsten film 7 is deposited on the outer surface of the Ti layer 5a and the TiN layer 6a, the tungsten nuclei generate more rapidly on the Ti material than on the TiN material. Thus, tungsten film 7 grows on the surface of the Ti layer 5a sooner than on the TiN layer 6a.
Accordingly, the resulting tungsten film is not uniformly deposited over both the Ti layer 5a and the TiN layer 6a. This nonuniform depositing of the tungsten makes it difficult to manufacture a reliable capacitor and adversely affects the reproducibility of the capacitor.